1. Field of the Invention
The present invention relates to a method for forming metal interconnections in a semiconductor device, and more particularly, to a method for forming a dual damascene structure in a low dielectric layer.
2. Description of the Related Art
To comply with the demand for highly integrated semiconductor devices, multilayered conductive layers are formed on a substrate, and the size of the multilayered conductive layer becomes smaller. If the multilayered conductive layer having a fine size is formed on the substrate, resistance and parasitic capacitance between layers increase, and thus resistance-capacitance (RC) delay occurs in devices.
In order to prevent RC delay, at the present, a low-K dielectric insulating layer is used as an interlevel dielectric (ILD) layer, and copper having low resistance is used as a metal interconnection material. As is well known, since it is difficult to directly etch a copper metal layer, a dual damascene process is used in the case where the copper metal layer is used for the interconnection.
Hereinafter, a conventional method for forming a dual damascene structure using a low dielectric insulating layer as an ILD layer will be described with reference to FIGS. 1A through 1F.
As shown in FIG. 1A, an underlying layer 10 including a contact plug 20 is formed on a semiconductor substrate 10 on which a semiconductor device is formed. An underlying hard mask layer 17 may be formed on the surface of the underlying layer 10. A barrier layer 22, a first organic polymer layer 25, an etch stopper 28, and a second organic polymer layer 30 are sequentially formed on the underlying hard mask layer 17 and the contact plug 20. Here, the first organic polymer layer 25 is a via level insulating layer in which a via hole is to be formed, and the second organic polymer layer 30 is a trench level insulating layer in which a trench is to be formed.
Subsequently, a first hard mask layer 33 and a second hard mask layer 35 are sequentially stacked on the second organic polymer layer 30. In such a case, the first and second hard mask layers 33 and 35 are provided as an etching mask for etching the first and second organic polymer layers 25 and 30.
As shown in FIG. 1B, a first photoresist pattern 38 for defining a trench is formed on the second hard mask layer 35. The second hard mask layer 35 is patterned in the form of the first photoresist pattern 38. Here, X1 denotes an interval between the first photoresist patterns 38 and becomes a line width of a predetermined trench.
As shown in FIG. 1C, the first photoresist pattern 38 is removed. A second photoresist pattern 40 is formed on the second and first hard mask layers 33 and 35. Here, an interval X2 between the second photoresist patterns 40 is narrower than the interval X1 between the first photoresist patterns 38 (see FIG. 1B) and may be preferably about the same as that of the contact plug 20. Here, the interval X2 becomes the diameter of a predetermined via hole. As a result, the second hard mask layer 35 becomes a mask for defining a trench, and the first hard mask layer 33 becomes a mask for defining a via hole. After that, the first hard mask layer 33 exposed by the second photoresist pattern 40 is etched.
Referring to FIG. 1D, the second photoresist pattern 40 is removed. The exposed second organic polymer layer 30 is patterned in the form of the first hard mask layer 33.
After that, as shown in FIG. 1E, an exposed etch stopper 28 is etched using the patterned second organic polymer layer 30 as a mask, and simultaneously the first hard mask layer 33 under the second hard mask layer 35 is etched in the form of the second hard mask layer 35. As a result, the etch stopper 28 has an interval of the diameter of a via hole, and the first and second hard mask layers 33 and 35 have intervals of the line width of a trench. After that, the exposed second organic polymer layer 30 is etched using the first and second hard mask layers 33 and 35 as a mask, and simultaneously the exposed first organic polymer layer 30 is etched using the etch stopper 28 as a mask. As a result, a trench t having the line width of the interval X1 is formed on the second organic polymer layer 30, and a via hole h, which is connected to the trench t and has the line width smaller than that of the trench t, is formed on the first organic polymer layer 25. As shown in FIG. 1F, the barrier layer 22 and the etch stopper 28, which are exposed by the via hole h and the trench t, respectively, are partially removed, thereby completing a dual damascene structure. When the barrier layer 22 and the etch stopper 28 are removed, the second hard mask layer 33 may be simultaneously removed. Here, for performing a subsequent CMP process, the first hard mask layer 33 must remain on the second organic polymer layer 30.
Although not shown, a copper metal layer is deposited on a semiconductor substrate structure so that the damascene structure is sufficiently buried, and then a chemical mechanical polishing (CMP) process is performed so that the first hard mask layer 33 is exposed, thereby forming a damascene metal interconnection.
However, in the conventional method for forming a dual damascene structure, an ILD layer in which the dual damascene structure is formed is formed as an organic polymer layer, resulting in the following problems.
In the prior art, since etching selectivity with respect to an organic polymer layer and a photoresist pattern is similar, a hard mask layer such as a silicon carbide (SiC) layer or a silicon oxide (SiO2) layer, instead of a photoresist layer is used as a mask for etching the organic polymer layer. However, as shown in FIG. 1E, in the case where the first hard mask layer 33 is etched using the second hard mask layer 35, etching selectivity with respect to the first and second hard mask layers 33 and 35 is similar, parts of the second and first hard mask layers 35 and 33 may be lost. Likewise, if the parts of the second and first hard mask layers 35 and 33 are lost, a hard mask layer for etching the organic polymer layer may be transformed. As a result, if the second organic polymer layer 30 is etched using hard mask layers having a transformed shape, as shown in FIG. 2, the remaining first hard mask layer 33 and the second organic polymer layer 30 are transformed into a peak having incline. Thus, after a metal layer such as copper is buried in the trench t and the via hole h, the width of the remaining first hard mask layer 33 becomes very narrow during a CMP process, and thus a Cu metal layer having a damascene shape is not separated from another adjacent Cu metal layer having a damascene shape.
Also, in the prior art, since the organic polymer layer is used as an ILD layer, it is difficult to obtain the mechanical strength of the ILD layer during a subsequent CMP process. Further, since the dielectric constant of the organic polymer layer is low, it is difficult to easily disperse joule heat occurring when metal interconnection formed in the organic polymer layer electrically conducts.
Thus, a technique for forming a part of the ILD layer as a silicon oxide layer having a high dielectric constant has been suggested as another method according to the prior art and will be described with reference to FIGS. 3A through 3D.
As shown in FIG. 3A, an underlying layer 55 including a contact plug 60 is formed on a semiconductor substrate 50 on which a semiconductor device (not shown) is formed. An underlying hard mask layer 57 is formed on the surface of the underlying layer 55. A barrier layer 62, a silicon oxide layer 65, and an organic polymer layer 70 are sequentially formed on the underlying hard mask layer 57 and the contact plug 60. Here, the silicon oxide layer 65 becomes an ILD layer having a via level, and the organic polymer layer 70 becomes an insulating layer having a trench level. Next, a first hard mask layer 75 and a second hard mask layer 80 are sequentially stacked. In such a case, as described previously, a silicon carbide layer may be used as the first hard mask layer 75, and a silicon oxide layer may be used as the second hard mask layer 80. A first photoresist pattern (not shown) for defining a trench is formed on the second hard mask layer 80, and then the second hard mask layer 80 is etched in the form of the first photoresist pattern. Next, the first photoresist pattern is removed, and then a second photoresist pattern (not shown) for defining a via hole is formed on the second and first hard mask layers 80 and 75. Here, an interval between the second photoresist patterns is narrower than the interval between the first photoresist patterns and may be preferably about the same as that of the contact plug 60. The first hard mask layer 75 exposed by the second photoresist pattern is, etched. After that, the second photoresist pattern is removed.
As shown in FIG. 3B, the organic polymer layer 70 is etched using the first hard mask layer 75 as a mask.
After that, as shown in FIG. 3C, the first hard mask layer 75 is etched in the form of the second hard mask layer 80. Simultaneously, the silicon oxide layer 65 having a similar etching selectivity to that of the second hard mask layer 80 is also etched using the organic polymer layer 70 as a mask, thereby forming a via hole h.
As shown in FIG. 3D, the organic polymer layer 70 is etched in the form of the first and second hard mask layers 75 and 80 to form a trench t, thereby forming a dual damascene contact hole having the trench t and the via hole h. Next, the exposed barrier layer 62 is etched. In such a case, the second hard mask layer 80 is also simultaneously removed when the barrier layer 62 is etched.
Although not shown, a copper metal layer is deposited on a semiconductor substrate structure so that the damascene structure is sufficiently buried, and then a chemical mechanical polishing (CMP) process is performed so that the first hard mask layer 75 is exposed, thereby forming a damascene metal interconnection.
In the above method, the silicon oxide layer is used as a part of the ILD layer, thereby improving the mechanical strength of the ILD layer and the joule heat dispersion property. However, etching the silicon oxide layer 65 for forming the via hole h is performed simultaneously with etching the first hard mask layer 75 using the second hard mask layer 80 as a mask, and thus the second and first hard mask layers 80 and 75 are substantially lost. That is, as described above, there is a wide difference between the thickness of the silicon oxide layer 65 used as the ILD layer and the thickness of the second hard mask layer 80, and thus the second and first hard mask layers 80 and 75 are substantially lost when the silicon oxide layer 65 for forming a via hole is etched. In this way, if the hard mask layers are substantially lost, as described above, a Cu metal layer having a damascene shape is not separated from another adjacent Cu metal layer having a damascene shape.
In addition, the silicon oxide layer (SiO2) having a high dielectric constant is used as the ILD layer, and thus the dielectric constant of the ILD layer increases, and parasitic capacitance may occur.
To solve the above problems, it is an object of the present invention to provide a method for forming a dual damascene structure in a semiconductor device, which is capable of preventing defects in node segregation between damascene interconnections and reducing parasitic capacitance.
According to one aspect of the present invention, there is provided a method for forming a dual damascene structure in a semiconductor device. An insulating structure layer including a via level insulating layer and a trench level insulating layer and a hard mask layer are deposited sequentially on a semiconductor substrate on which an underlying layer including a contact plug is formed. A via hole is formed on the via level insulating layer using the hard mask layer. A trench connected to the via hole is formed in the insulating structure layer using the hard mask layer. Here, a predetermined upper portion of the insulating structure layer and the hard mask layer are removed when the trench and the via hole are formed.
In one embodiment, the insulting structure layer further includes a trench level insulating layer, an etch stopper formed on the trench level insulating layer and a buffer insulating layer formed on the etch stopper, and the buffer insulating layer is removed when the trench is formed. Also, the trench level insulating layer and the buffer insulating layer are organic polymer layers.
According to another aspect of the present invention, there is provided a method for forming a dual damascene structure in a semiconductor device. A via level insulating layer, a trench level insulating layer, an etch stopper, a buffer insulating layer, a first hard mask layer, and a second hard mask layer are deposited sequentially on a semiconductor substrate on which an underlying layer including a contact plug is formed. The second hard mask layer is patterned to have a first interval, and the first hard mask layer is patterned to have a second interval narrower than the first interval. The buffer insulating layer is etched in the form of the first hard mask layer. The first hard mask layer is etched in the form of the second hard mask layer and simultaneously the etch stopper is etched in the form of the buffer insulating layer. The buffer insulating layer is etched again in the form of the second and first hard mask layers and simultaneously the trench level insulating layer is etched in the form of the etched etch stopper. A via hole is formed in the via level insulating layer by etching the via level insulating layer using the trench level insulating layer as a mask and simultaneously the etch stopper is etched again in the form of the buffer insulating layer. A trench is formed in the trench level insulating layer by etching the exposed trench level insulating layer by using the etch stopper as a mask. Here, when forming the via hole, the second and first hard mask layers are simultaneously removed, and when forming the trench, the buffer insulating layer is removed.
According to another aspect of the present invention, there is provided a method for forming a dual damascene structure in a semiconductor device. A via level insulating layer, a first organic polymer layer, an etch stopper, a second organic polymer layer, a first hard mask layer, and a second hard mask layer are deposited sequentially on a semiconductor substrate on which an underlying layer including a contact plug is formed. The second hard mask layer is patterned to have a first interval. The exposed first hard mask layer is patterned to have a second interval narrower than the first interval. The second organic polymer layer is etched in the form of the first hard mask layer. The first hard mask layer is etched in the form of the second hard mask layer and simultaneously the etch stopper is etched in the form of the etched second organic polymer layer. The second organic polymer layer is etched again in the form of the second and first hard mask layers and simultaneously the first organic polymer layer is etched by using the etch stopper as a mask. A via hole is formed in the via level insulating layer by etching the exposed via level insulating layer using the first organic polymer layer as a mask and simultaneously the etch stopper is etched again in the form of the etched second organic polymer layer. A trench is formed in the first organic polymer layer by etching the exposed first organic polymer layer using the etch stopper as a mask. Here, when forming the via hole, the second and first hard mask layers are simultaneously removed, and when forming the trench, the second organic polymer layer is removed, and the via level insulating layer is formed of a material selected from a SiOC:H layer, a SiOC layer, a HSQ layer, and porous silica.
Here, the etch stopper is formed of a silicon carbide layer, a silicon oxide layer, or a silicon nitride layer.
Also, the first and second hard mask layers are formed of materials having etching selectivity different from those of the first and second organic polymer layers and similar to that of the etch stopper.
Preferably, the first hard mask layer is formed of one of a silicon carbide layer, a silicon nitride layer, and a silicon oxide layer, and the second hard mask layer is formed of a silicon oxide layer in the case where the first hard mask layer is formed of a silicon carbide layer or a silicon nitride layer, and the second hard mask layer is formed of a silicon carbide layer or,a silicon nitride layer in the case where the first hard mask layer is formed of a silicon oxide layer.
Furthermore, the first interval is the diameter of the via hole, and the second interval is the line width of the trench.